This invention relates to phase locked loops, which are designed with two zeros/two poles active compensation.
A phase locked loop provides the means for generating an output signal whose frequency is a multiple of the input reference frequency (fref), in a manner that synchronizes (or locks) the relationship between the phases and frequencies of the input and output signals. The phase locked loop is a specialized form of a feedback control system. In this case, a voltage controlled oscillator (VCO) is used to multiply its input frequency by a factor of n to generate the output frequency (fout). In order to compare fout with the input reference frequency (fref), the VCO output is divided by n and then fed back to the VCO and loop filter compensation circuits through a phase detector. The phase detector produces a pulse error voltage on each rising edge of the reference signal that has a pulse width equal to the phase difference between the reference frequency (fref) and the output frequency divided by n, fout/n. The loop filter converts the pulsed error voltage to a DC voltage that is used to control the VCO. This DC control voltage causes the VCO to slightly change fout in a direction that reduces the phase difference between the two frequencies, thus also reducing the frequency difference between the input and output signals. This error correcting cycle is repeated for each reference frequency cycle period, ultimately resulting in a minimum difference between the two frequencies. The phase locked loop is described as xe2x80x9clockedxe2x80x9d when the phase difference between the two signals has stabilized.
A phase locked loop is considered to have three states of operation. The loop is in the unlocked state when power is first applied. It is in the acquisition state when the oscillators are being synchronized. Finally, it is in the locked state when fout/n is equal to the average fref and the period of fout/n has a fixed phase or locked relationship to the average fref period. This is achieved when the error reference signal reaches a steady state condition.
Presently, phase locked loops are commonly designed with one zero compensation in order to avoid stability problems associated with additional zeros. (A zero in a network function represents any real or complex value which when substituted for the Laplace transform s can cause the network transfer function to become zero. Therefore, in the transform function of the phase locked loop compensation circuit, the zero is visible as a function in the numerator which can have a value which will cause the transform function to become zero.) These phase locked loop designs typically utilize charge pumps and large capacitors when narrow loop bandwidths are required. (The charge pump in a phase locked loop implementation is essentially a current source that is controlled by the phase error, i.e. a pulsed current source.) The physical space required for the large capacitors associated with narrow loop bandwidth phase locked loops presently prevents the development of totally integrated circuit solutions for these charge pump based designs. Secondarily, the low output currents required from the charge pumps associated with these designs further limit the practicality of these implementations.
Similarly, phase locked loops with active filter compensation have not been totally achieved on integrated circuits because of the physical space previously required for the high performance operational amplifier (op amp) required for these circuits, as well as the physical size of required capacitors. (An active filter is defined as a filter with an op amp in the loop compensation circuit.)
Thus, designs for narrow loop bandwidth phase locked loops typically have a single zero and are implemented with discrete components or a combination of an integrated circuit resident charge pump and external resistors and capacitors. With the advances in op amp semiconductor technology and the utilization of two zeros/two poles compensation, it is now possible to incorporate the different total phase locked loop circuitry on a single integrated circuit device.
This invention provides active filter compensation phase locked loops designed with two zeros followed by two poles. A pole in a network function represents any real or complex value that can be substituted for the Laplace transform s, causing the network transfer function to be infinite. Thus, the number of poles in a network is determined by the number of terms in the denominator of the circuit""s transfer function that can have a value for s that will cause the transfer function to become infinite.
The addition of the second zero provides more phase compensation and thus greater stability for the phase locked loop. The op amp provides differential high gain amplification that cannot be achieved with a charge pump. The two poles provide two perfect integrators at the origin in the network transfer function in what is known as a Type 2 phased locked loop. One of these integrators comes from the active compensation circuit and the other is from the VCO. In keeping with phase locked loop standard practice, the pole provided by the VCO does not impact the invention. Therefore, further description of this pole is not necessary. In addition, two more high frequency poles in the active compensation circuit correct for the instability induced by the two zeros. The use of active filters with two zeros/two poles allows phase locked loops to be designed with narrower loop bandwidths and higher loop stability than can be accomplished utilizing the typical single zero, charge pump compensation method.
In addition, this invention results in designs that can be totally incorporated on integrated circuits. This is possible for two reasons. First, the invention results in designs with smaller sized capacitors than typically utilized with charge pump based phased locked loops for a specific frequency. Secondarily, the invention utilizes state-of-the-art high performance op amps that are now feasible on integrated circuits as a result of capacitor metal oxide semiconductor (CMOS) technology advances.
The phase locked loop with two poles/two zeros active compensation is comprised of circuit elements which are characteristic of all phase locked loops. These are a phase detector, VCO, and programmable divider. The input to the phase locked loop is a signal with input voltage level operating at a reference frequency (fref); the output from the phase locked loop has a frequency fout=nxc2x7fref. The two poles/two zeros active compensation circuit of the phase locked loop is typically achieved with a combination of resistors, capacitors, and operational amplifier.
Equations are developed for synthesis of the two zeros/two pole active compensation phase locked loop based upon assumptions for initial circuit parameters such as reference frequency, voltage controlled oscillator gain, feedback divide ratio, damping factor, desired loop bandwidth, and desired phase detector gain.